Routing
Routing converts logical connections into legal metal and via shapes across the chip's routing layers.
Global routing plans capacity; detailed routing creates exact rule-compliant shapes and exposes real parasitic delay.
A long net may move to a higher metal layer with lower resistance, but it then requires vias and competes for scarce upper-layer resources.
Physical Design flow
Follow each stage in sequence. Every stage produces information needed by the next.
Routing—visualized
This technical view uses the actual structures and relationships associated with this stage, followed by its key terms.
Understand every concept
Global routing
What it is: Global routing is a core concept within Routing. It describes the information, structure, or analysis engineers use at this stage of the Physical Design flow.
Why it matters: Understanding it helps you interpret the stage correctly, avoid incorrect assumptions, and connect the result to the next implementation or signoff step.
Where it fits: This topic belongs to module 6, Routing, and its output supports the stages that follow.
Practical example: Engineer workflow: Run global routing and study demand-versus-capacity maps. A long net may move to a higher metal layer with lower resistance, but it then requires vias and competes for scarce upper-layer resources.
Detailed routing
What it is: Detailed routing is a core concept within Routing. It describes the information, structure, or analysis engineers use at this stage of the Physical Design flow.
Why it matters: Understanding it helps you interpret the stage correctly, avoid incorrect assumptions, and connect the result to the next implementation or signoff step.
Where it fits: This topic belongs to module 6, Routing, and its output supports the stages that follow.
Practical example: Engineer workflow: Perform track assignment and detailed routing. A long net may move to a higher metal layer with lower resistance, but it then requires vias and competes for scarce upper-layer resources.
Parasitic extraction
What it is: Parasitic extraction is a core concept within Routing. It describes the information, structure, or analysis engineers use at this stage of the Physical Design flow.
Why it matters: Understanding it helps you interpret the stage correctly, avoid incorrect assumptions, and connect the result to the next implementation or signoff step.
Where it fits: This topic belongs to module 6, Routing, and its output supports the stages that follow.
Practical example: Engineer workflow: Repair DRC, antenna, transition, and signal-integrity issues. A long net may move to a higher metal layer with lower resistance, but it then requires vias and competes for scarce upper-layer resources.
Work through it step by step
- 1
Global routing
Run global routing and study demand-versus-capacity maps.
- 2
Detailed routing
Perform track assignment and detailed routing.
- 3
Parasitic extraction
Repair DRC, antenna, transition, and signal-integrity issues.
- 4
Global routing
Extract parasitics and optimize post-route timing.
Explore each topic
01Global routing
Understand the concept, connect it to the ASIC flow, study the report or behavior it produces, and apply it in a guided exercise. Check the result against the module goal before moving forward.
02Detailed routing
Understand the concept, connect it to the ASIC flow, study the report or behavior it produces, and apply it in a guided exercise. Check the result against the module goal before moving forward.
03Parasitic extraction
Understand the concept, connect it to the ASIC flow, study the report or behavior it produces, and apply it in a guided exercise. Check the result against the module goal before moving forward.
Completion checklist
- ✓ No opens or shorts
- ✓ Routing DRC is clean
- ✓ Antenna risk is resolved
- ✓ Extracted timing is within targets
Practise with open-source tools
These are official third-party GitHub projects selected for this learning path.