Floorplanning
Floorplanning defines the die, core, macro arrangement, utilization, and routing space that every later stage must work within.
A good floorplan balances area cost with enough room for routing, clock buffers, power structures, and timing optimization.
With 4.8 mm² of standard-cell area and a 70% utilization target, the initial core area estimate is 4.8/0.70 = 6.86 mm² before macro and margin refinement.
Physical Design flow
Follow each stage in sequence. Every stage produces information needed by the next.
Floorplanning—visualized
This technical view uses the actual structures and relationships associated with this stage, followed by its key terms.
Die and core—see the difference
The die is the complete manufactured chip boundary. The core is the inner working region used for logic placement. The gap around the core supports power distribution, I/O access, and manufacturing structures.
Understand every concept
Die area
What it is: The die is the complete rectangular piece of silicon cut from the wafer. It contains the core, I/O structures, power delivery, seal ring, and manufacturing margins.
Why it matters: Die area directly affects manufacturing cost and the number of chips that fit on a wafer. Making it too small creates routing and power problems; making it too large wastes silicon.
Where it fits: This topic belongs to module 2, Floorplanning, and its output supports the stages that follow.
Practical example: A 3.0 mm × 2.5 mm die has a total area of 7.5 mm², including everything inside the outer boundary.
Core area
What it is: The core is the inner placeable region where standard cells and most hard macros are arranged. It sits inside the die boundary.
Why it matters: Core dimensions determine utilization, average wire length, congestion, clock reach, and the space available for optimization cells.
Where it fits: This topic belongs to module 2, Floorplanning, and its output supports the stages that follow.
Practical example: If the core is 2.6 mm × 2.6 mm, its area is 6.76 mm². The surrounding die-to-core margin can carry power rings and I/O connections.
Standard cells
What it is: Standard cells are pre-designed library elements such as NAND gates, multiplexers, buffers, and flip-flops. They share a fixed row height and vary in width.
Why it matters: Synthesis maps RTL into standard-cell instances. Placement later positions thousands or millions of these instances on legal rows inside the core.
Where it fits: This topic belongs to module 2, Floorplanning, and its output supports the stages that follow.
Practical example: A timing-critical path may use stronger drive cells, while noncritical logic can use smaller cells to reduce area and power.
Hard macros
What it is: Hard macros are fixed-layout blocks such as SRAMs, ROMs, PLLs, or analog IP. Their internal geometry cannot be changed by the place-and-route tool.
Why it matters: Macros are large routing obstacles. Their position and pin orientation strongly affect wire length, congestion, power access, and timing.
Where it fits: This topic belongs to module 2, Floorplanning, and its output supports the stages that follow.
Practical example: An SRAM connected heavily to a processor block should be placed nearby with its signal pins facing the logic when practical.
Macro halo
What it is: A halo is a keepout margin around a macro where standard cells cannot be placed.
Why it matters: The empty margin leaves routing access around dense macro pins and prevents cells from blocking connections at the macro boundary.
Where it fits: This topic belongs to module 2, Floorplanning, and its output supports the stages that follow.
Practical example: A macro may use a 3 µm halo on three sides and a wider channel on the pin-dense side.
Utilization
What it is: Utilization describes how much placeable core area is occupied by standard cells before later buffers, fillers, decaps, and ECO cells are added.
Why it matters: High utilization reduces area but increases congestion and makes timing closure harder. Low utilization improves freedom but can increase die cost and wire length.
Where it fits: This topic belongs to module 2, Floorplanning, and its output supports the stages that follow.
Practical example: A common starting target is about 60–75%, then adjusted for macro density, routing layers, design style, and process requirements.
Aspect ratio
What it is: Aspect ratio compares core height with core width. A value of 1.0 represents a square core.
Why it matters: Extreme shapes increase long-distance connections and can make clock, power, and routing distribution uneven.
Where it fits: This topic belongs to module 2, Floorplanning, and its output supports the stages that follow.
Practical example: A 2.4 mm × 2.4 mm core has AR=1.0; a 3.6 mm × 1.2 mm core has AR=0.33 when height is divided by width.
Channels and blockages
What it is: Channels are reserved gaps between macros; placement or routing blockages restrict where cells or wires may be created.
Why it matters: They protect routing corridors, prevent local density spikes, and guide the tools away from regions with limited capacity.
Where it fits: This topic belongs to module 2, Floorplanning, and its output supports the stages that follow.
Practical example: Two macros with facing pin banks need a wide enough channel for signal routes plus power straps and via access.
Core formulas
Standard-cell area ÷ placeable core area × 100%Standard-cell area ÷ target utilizationCore height ÷ core widthGiven standard-cell area = 4.8 mm² and target utilization = 70%:
Required core area = 4.8 ÷ 0.70 = 6.86 mm²For a square core, width and height are approximately √6.86 = 2.62 mm. Then add macro area, halos, routing channels, and the die-to-core margin before finalizing the floorplan.
Work through it step by step
- 1
Die and core sizing
Estimate core area from standard-cell and macro area.
- 2
Macro placement
Choose a practical aspect ratio and target utilization.
- 3
Utilization and aspect ratio
Place macros by connectivity with halos and channels.
- 4
Die and core sizing
Run early congestion and timing checks before committing.
Explore each topic
01Die and core sizing
Understand the concept, connect it to the ASIC flow, study the report or behavior it produces, and apply it in a guided exercise. Check the result against the module goal before moving forward.
02Macro placement
Understand the concept, connect it to the ASIC flow, study the report or behavior it produces, and apply it in a guided exercise. Check the result against the module goal before moving forward.
03Utilization and aspect ratio
Understand the concept, connect it to the ASIC flow, study the report or behavior it produces, and apply it in a guided exercise. Check the result against the module goal before moving forward.
Completion checklist
- ✓ Macros have routing access
- ✓ Utilization leaves optimization space
- ✓ Aspect ratio supports connectivity
- ✓ No severe early congestion hot spots
Practise with open-source tools
These are official third-party GitHub projects selected for this learning path.