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Module 16 min

Introduction to Physical Design

Physical design converts a synthesized gate-level netlist into geometric layout data that a foundry can manufacture.

◉ Banzs Tip

The backend flow decides where cells sit, how power and clocks reach them, and how every signal is routed while meeting timing and manufacturing rules.

A logical NAND instance in the netlist becomes a specific standard-cell rectangle placed on a legal row and connected through metal layers to its drivers and loads.

Physical Design flow

Follow each stage in sequence. Every stage produces information needed by the next.

Introduction to Physical Design—visualized

This technical view uses the actual structures and relationships associated with this stage, followed by its key terms.

Understand every concept

01

Netlist to layout

What it is: Netlist to layout is a core concept within Introduction to Physical Design. It describes the information, structure, or analysis engineers use at this stage of the Physical Design flow.

Why it matters: Understanding it helps you interpret the stage correctly, avoid incorrect assumptions, and connect the result to the next implementation or signoff step.

Where it fits: This topic belongs to module 1, Introduction to Physical Design, and its output supports the stages that follow.

Practical example: Engineer workflow: Collect the mapped netlist, timing constraints, libraries, and technology data. A logical NAND instance in the netlist becomes a specific standard-cell rectangle placed on a legal row and connected through metal layers to its drivers and loads.

02

Backend flow stages

What it is: Backend flow stages is a core concept within Introduction to Physical Design. It describes the information, structure, or analysis engineers use at this stage of the Physical Design flow.

Why it matters: Understanding it helps you interpret the stage correctly, avoid incorrect assumptions, and connect the result to the next implementation or signoff step.

Where it fits: This topic belongs to module 1, Introduction to Physical Design, and its output supports the stages that follow.

Practical example: Engineer workflow: Create the floorplan and power-delivery foundation. A logical NAND instance in the netlist becomes a specific standard-cell rectangle placed on a legal row and connected through metal layers to its drivers and loads.

03

Inputs and outputs

What it is: Inputs and outputs is a core concept within Introduction to Physical Design. It describes the information, structure, or analysis engineers use at this stage of the Physical Design flow.

Why it matters: Understanding it helps you interpret the stage correctly, avoid incorrect assumptions, and connect the result to the next implementation or signoff step.

Where it fits: This topic belongs to module 1, Introduction to Physical Design, and its output supports the stages that follow.

Practical example: Engineer workflow: Place cells, build the clock tree, and route every connection. A logical NAND instance in the netlist becomes a specific standard-cell rectangle placed on a legal row and connected through metal layers to its drivers and loads.

Work through it step by step

  1. 1

    Netlist to layout

    Collect the mapped netlist, timing constraints, libraries, and technology data.

  2. 2

    Backend flow stages

    Create the floorplan and power-delivery foundation.

  3. 3

    Inputs and outputs

    Place cells, build the clock tree, and route every connection.

  4. 4

    Netlist to layout

    Run extracted timing and physical signoff before GDSII release.

Explore each topic

01

Netlist to layout

Understand the concept, connect it to the ASIC flow, study the report or behavior it produces, and apply it in a guided exercise. Check the result against the module goal before moving forward.

02

Backend flow stages

Understand the concept, connect it to the ASIC flow, study the report or behavior it produces, and apply it in a guided exercise. Check the result against the module goal before moving forward.

03

Inputs and outputs

Understand the concept, connect it to the ASIC flow, study the report or behavior it produces, and apply it in a guided exercise. Check the result against the module goal before moving forward.

Completion checklist

  • Netlist and constraints are consistent
  • Technology views load correctly
  • Every flow stage has defined outputs
  • Signoff criteria are known before implementation

Practise with open-source tools

These are official third-party GitHub projects selected for this learning path.

See all curated resources →