Physical Verification
Physical verification confirms that the routed layout follows foundry geometry rules and matches the intended electrical netlist.
DRC asks whether geometry is manufacturable; LVS asks whether layout connectivity matches the source design.
A missing via may create an LVS open even when the two metal shapes look aligned in the layout viewer.
Physical Design flow
Follow each stage in sequence. Every stage produces information needed by the next.
Physical Verification—visualized
This technical view uses the actual structures and relationships associated with this stage, followed by its key terms.
Understand every concept
DRC and LVS
What it is: DRC and LVS is a core concept within Physical Verification. It describes the information, structure, or analysis engineers use at this stage of the Physical Design flow.
Why it matters: Understanding it helps you interpret the stage correctly, avoid incorrect assumptions, and connect the result to the next implementation or signoff step.
Where it fits: This topic belongs to module 7, Physical Verification, and its output supports the stages that follow.
Practical example: Engineer workflow: Run the qualified DRC rule deck. A missing via may create an LVS open even when the two metal shapes look aligned in the layout viewer.
Antenna checks
What it is: Antenna checks is a core concept within Physical Verification. It describes the information, structure, or analysis engineers use at this stage of the Physical Design flow.
Why it matters: Understanding it helps you interpret the stage correctly, avoid incorrect assumptions, and connect the result to the next implementation or signoff step.
Where it fits: This topic belongs to module 7, Physical Verification, and its output supports the stages that follow.
Practical example: Engineer workflow: Extract layout connectivity and devices. A missing via may create an LVS open even when the two metal shapes look aligned in the layout viewer.
Manufacturing readiness
What it is: Manufacturing readiness is a core concept within Physical Verification. It describes the information, structure, or analysis engineers use at this stage of the Physical Design flow.
Why it matters: Understanding it helps you interpret the stage correctly, avoid incorrect assumptions, and connect the result to the next implementation or signoff step.
Where it fits: This topic belongs to module 7, Physical Verification, and its output supports the stages that follow.
Practical example: Engineer workflow: Compare the extracted netlist with the source. A missing via may create an LVS open even when the two metal shapes look aligned in the layout viewer.
Work through it step by step
- 1
DRC and LVS
Run the qualified DRC rule deck.
- 2
Antenna checks
Extract layout connectivity and devices.
- 3
Manufacturing readiness
Compare the extracted netlist with the source.
- 4
DRC and LVS
Resolve antenna and electrical-rule issues, then rerun signoff.
Explore each topic
01DRC and LVS
Understand the concept, connect it to the ASIC flow, study the report or behavior it produces, and apply it in a guided exercise. Check the result against the module goal before moving forward.
02Antenna checks
Understand the concept, connect it to the ASIC flow, study the report or behavior it produces, and apply it in a guided exercise. Check the result against the module goal before moving forward.
03Manufacturing readiness
Understand the concept, connect it to the ASIC flow, study the report or behavior it produces, and apply it in a guided exercise. Check the result against the module goal before moving forward.
Completion checklist
- ✓ DRC has no unapproved errors
- ✓ LVS reports a clean match
- ✓ Antenna checks pass
- ✓ Final runs use release data
Practise with open-source tools
These are official third-party GitHub projects selected for this learning path.