Synthesis
Yosys
Open-source RTL synthesis framework for Verilog designs, technology mapping, netlist generation, and custom synthesis flows.
Use it to
Open official GitHub repository ↗Synthesize learning projects and inspect how RTL becomes gates.
BANZSASIC FLOW WORKSHOP← BackAsk a mentorCurated open-source tools
GitHub resources for the ASIC flow.
Official repositories selected for practical RTL, verification, synthesis, physical-design, timing, and layout learning. These third-party projects are not owned by Banzs Team.
RTL simulation & lint
Verilator
Fast open-source SystemVerilog simulator and lint system used for design checking and high-performance simulation.
Use it to
Open official GitHub repository ↗Lint RTL, compile test environments, and run fast simulations.
Verification
cocotb
Python-based verification framework for writing reusable testbenches that run with common HDL simulators.
Use it to
Open official GitHub repository ↗Build readable drivers, monitors, scoreboards, and regression tests in Python.
RTL simulation
Icarus Verilog
Widely used open-source Verilog compiler and simulator suited to learning, small projects, and automated testing.
Use it to
Open official GitHub repository ↗Compile Verilog and inspect waveforms during early RTL practice.
Formal verification
SymbiYosys
Front end for Yosys-based formal verification flows supporting bounded, prove, cover, and liveness tasks.
Use it to
Open official GitHub repository ↗Prove assertions and explore corner cases that simulation may miss.
Physical design
OpenROAD
Unified open-source physical-design application covering major implementation stages from floorplanning through detailed routing.
Use it to
Open official GitHub repository ↗Study floorplan, placement, CTS, routing, extraction, timing, and implementation reports.
RTL to GDSII
OpenROAD Flow Scripts
Reference automation and designs for running an end-to-end RTL-to-GDSII flow with OpenROAD and related tools.
Use it to
Open official GitHub repository ↗Understand stage handoffs, configuration, reproducible runs, and QoR comparisons.
RTL to GDSII
OpenLane 2
Modular next-generation OpenLane flow for orchestrating open-source ASIC implementation steps.
Use it to
Open official GitHub repository ↗Run a configurable educational flow and inspect artifacts produced at each stage.
Static timing analysis
OpenSTA
Open-source static timing engine supporting industry-standard timing concepts and formats.
Use it to
Open official GitHub repository ↗Read timing paths, experiment with constraints, and study setup/hold behavior.
Layout & DRC
Magic
Open-source VLSI layout system with interactive editing and design-rule checking capabilities.
Use it to
Open official GitHub repository ↗Inspect layouts, understand layers, and practise physical-rule debugging.
Layout inspection
KLayout
Powerful open-source layout viewer and editor with scripting and verification support.
Use it to
Open official GitHub repository ↗Explore GDS/OASIS hierarchy, measure geometry, and build layout-analysis scripts.