RTL to GDSII
Connect specification, RTL, synthesis, timing, physical implementation and signoff in one end-to-end course.
- Synthesizable RTL and constraints
- Synthesis QoR and netlist handoff
- Floorplan through routing
- Timing and physical signoff
BANZSASIC FLOW WORKSHOP← BackContact usCourses
Intermediate ASIC courses built around real flow decisions.
Move beyond definitions with structured modules, guided labs, reports and engineering checkpoints across the ASIC lifecycle.
LEVELFoundation → IntermediateFORMAT4–10 weeksLEARNING MODEConcept + practice
Choose your focus
Intermediate content with a clear next action.
Each option includes technical topics, applied practice and a direct path to continue learning.
Physical Design Intermediate
Build practical judgment for floorplan quality, congestion, power integrity, clock trees and routing closure.
- Macro placement and utilization
- Power rings, straps and rails
- Placement and CTS optimization
- Routing, IR drop and ECOs
STA & Constraints
Read timing reports, define clocks and I/O delays, and debug setup and hold failures across corners.
- Arrival, required time and slack
- Generated clocks and exceptions
- PVT, OCV and MMMC
- Timing ECO selection
How to use this page
Learn, apply and verify.
- 1
Guided lab
Apply the module to a small design and record inputs, commands, reports and conclusions.
- 2
Checkpoint review
Use a signoff-style checklist before advancing to the next flow stage.
- 3
160 assignments
Test each skill with instant correct/wrong feedback and explanations.
160 INTERACTIVE QUESTIONS
Open assignments →Check your understanding immediately.
Choose an answer, see correct responses in green, incorrect responses in red, and learn from the explanation.
Continue with Banzs Team.
Tell us what you want to learn, practise, or prepare for.
asicflowworkshop@gmail.com