Verification setup
Physical verification compares the final layout against foundry rules and the intended electrical netlist.
Correct runsets, layer maps, hierarchy, and source data are prerequisites for meaningful results.
If VDD is named VDD! in layout but VDD in the source, power-net mapping must reconcile them before LVS comparison.
Physical Verification flow
Follow each stage in sequence. Every stage produces information needed by the next.
Verification setup—visualized
This technical view uses the actual structures and relationships associated with this stage, followed by its key terms.
Understand every concept
Foundry decks and runsets
What it is: Foundry decks and runsets is a core concept within Verification setup. It describes the information, structure, or analysis engineers use at this stage of the Physical Verification flow.
Why it matters: Understanding it helps you interpret the stage correctly, avoid incorrect assumptions, and connect the result to the next implementation or signoff step.
Where it fits: This topic belongs to module 1, Verification setup, and its output supports the stages that follow.
Practical example: Engineer workflow: Select the foundry-qualified rule deck. If VDD is named VDD! in layout but VDD in the source, power-net mapping must reconcile them before LVS comparison.
Layout and netlist inputs
What it is: Layout and netlist inputs is a core concept within Verification setup. It describes the information, structure, or analysis engineers use at this stage of the Physical Verification flow.
Why it matters: Understanding it helps you interpret the stage correctly, avoid incorrect assumptions, and connect the result to the next implementation or signoff step.
Where it fits: This topic belongs to module 1, Verification setup, and its output supports the stages that follow.
Practical example: Engineer workflow: Provide layout, source netlist, and layer mapping. If VDD is named VDD! in layout but VDD in the source, power-net mapping must reconcile them before LVS comparison.
Hierarchy and black boxes
What it is: Hierarchy and black boxes is a core concept within Verification setup. It describes the information, structure, or analysis engineers use at this stage of the Physical Verification flow.
Why it matters: Understanding it helps you interpret the stage correctly, avoid incorrect assumptions, and connect the result to the next implementation or signoff step.
Where it fits: This topic belongs to module 1, Verification setup, and its output supports the stages that follow.
Practical example: Engineer workflow: Configure hierarchy, black boxes, and power names. If VDD is named VDD! in layout but VDD in the source, power-net mapping must reconcile them before LVS comparison.
Work through it step by step
- 1
Foundry decks and runsets
Select the foundry-qualified rule deck.
- 2
Layout and netlist inputs
Provide layout, source netlist, and layer mapping.
- 3
Hierarchy and black boxes
Configure hierarchy, black boxes, and power names.
- 4
Foundry decks and runsets
Run a small validation before the full signoff job.
Explore each topic
01Foundry decks and runsets
Understand the concept, connect it to the ASIC flow, study the report or behavior it produces, and apply it in a guided exercise. Check the result against the module goal before moving forward.
02Layout and netlist inputs
Understand the concept, connect it to the ASIC flow, study the report or behavior it produces, and apply it in a guided exercise. Check the result against the module goal before moving forward.
03Hierarchy and black boxes
Understand the concept, connect it to the ASIC flow, study the report or behavior it produces, and apply it in a guided exercise. Check the result against the module goal before moving forward.
Completion checklist
- ✓ Deck version matches the process
- ✓ Top cell is correct
- ✓ Units and layer maps match
- ✓ Black boxes are intentional
Practise with open-source tools
These are official third-party GitHub projects selected for this learning path.