LVS
LVS extracts devices and connectivity from layout and compares them with the source netlist.
Debug topology first—power, shorts, opens, and hierarchy—before chasing individual device-property mismatches.
One missing contact can create an open net that appears as many downstream mismatches; fixing the first open may clear the entire group.
Physical Verification flow
Follow each stage in sequence. Every stage produces information needed by the next.
LVS—visualized
This technical view uses the actual structures and relationships associated with this stage, followed by its key terms.
Understand every concept
Extraction and comparison
What it is: Extraction and comparison is a core concept within LVS. It describes the information, structure, or analysis engineers use at this stage of the Physical Verification flow.
Why it matters: Understanding it helps you interpret the stage correctly, avoid incorrect assumptions, and connect the result to the next implementation or signoff step.
Where it fits: This topic belongs to module 3, LVS, and its output supports the stages that follow.
Practical example: Engineer workflow: Confirm source and layout top cells. One missing contact can create an open net that appears as many downstream mismatches; fixing the first open may clear the entire group.
Shorts and opens
What it is: Shorts and opens is a core concept within LVS. It describes the information, structure, or analysis engineers use at this stage of the Physical Verification flow.
Why it matters: Understanding it helps you interpret the stage correctly, avoid incorrect assumptions, and connect the result to the next implementation or signoff step.
Where it fits: This topic belongs to module 3, LVS, and its output supports the stages that follow.
Practical example: Engineer workflow: Resolve global power and ground naming. One missing contact can create an open net that appears as many downstream mismatches; fixing the first open may clear the entire group.
Device mismatches
What it is: Device mismatches is a core concept within LVS. It describes the information, structure, or analysis engineers use at this stage of the Physical Verification flow.
Why it matters: Understanding it helps you interpret the stage correctly, avoid incorrect assumptions, and connect the result to the next implementation or signoff step.
Where it fits: This topic belongs to module 3, LVS, and its output supports the stages that follow.
Practical example: Engineer workflow: Debug shorts and opens from the first divergence. One missing contact can create an open net that appears as many downstream mismatches; fixing the first open may clear the entire group.
Work through it step by step
- 1
Extraction and comparison
Confirm source and layout top cells.
- 2
Shorts and opens
Resolve global power and ground naming.
- 3
Device mismatches
Debug shorts and opens from the first divergence.
- 4
Extraction and comparison
Resolve missing, extra, or parameter-mismatched devices.
Explore each topic
01Extraction and comparison
Understand the concept, connect it to the ASIC flow, study the report or behavior it produces, and apply it in a guided exercise. Check the result against the module goal before moving forward.
02Shorts and opens
Understand the concept, connect it to the ASIC flow, study the report or behavior it produces, and apply it in a guided exercise. Check the result against the module goal before moving forward.
03Device mismatches
Understand the concept, connect it to the ASIC flow, study the report or behavior it produces, and apply it in a guided exercise. Check the result against the module goal before moving forward.
Completion checklist
- ✓ Net counts are reasonable
- ✓ Power nets correspond
- ✓ No unexpected black boxes
- ✓ Extracted and source schematics match
Practise with open-source tools
These are official third-party GitHub projects selected for this learning path.