DRC
DRC checks geometric layout rules that protect manufacturability and yield.
Every violation has a geometric context: width, spacing, enclosure, density, pattern, or interaction between layers.
A via enclosure error means the surrounding metal does not extend far enough beyond the via cut for reliable fabrication.
Physical Verification flow
Follow each stage in sequence. Every stage produces information needed by the next.
DRC—visualized
This technical view uses the actual structures and relationships associated with this stage, followed by its key terms.
Understand every concept
Width, spacing and enclosure
What it is: Width, spacing and enclosure is a core concept within DRC. It describes the information, structure, or analysis engineers use at this stage of the Physical Verification flow.
Why it matters: Understanding it helps you interpret the stage correctly, avoid incorrect assumptions, and connect the result to the next implementation or signoff step.
Where it fits: This topic belongs to module 2, DRC, and its output supports the stages that follow.
Practical example: Engineer workflow: Group violations by rule and repeated location pattern. A via enclosure error means the surrounding metal does not extend far enough beyond the via cut for reliable fabrication.
Density checks
What it is: Density checks is a core concept within DRC. It describes the information, structure, or analysis engineers use at this stage of the Physical Verification flow.
Why it matters: Understanding it helps you interpret the stage correctly, avoid incorrect assumptions, and connect the result to the next implementation or signoff step.
Where it fits: This topic belongs to module 2, DRC, and its output supports the stages that follow.
Practical example: Engineer workflow: Inspect the shapes and neighboring layers. A via enclosure error means the surrounding metal does not extend far enough beyond the via cut for reliable fabrication.
Violation debugging
What it is: Violation debugging is a core concept within DRC. It describes the information, structure, or analysis engineers use at this stage of the Physical Verification flow.
Why it matters: Understanding it helps you interpret the stage correctly, avoid incorrect assumptions, and connect the result to the next implementation or signoff step.
Where it fits: This topic belongs to module 2, DRC, and its output supports the stages that follow.
Practical example: Engineer workflow: Fix the generating placement or routing cause when possible. A via enclosure error means the surrounding metal does not extend far enough beyond the via cut for reliable fabrication.
Work through it step by step
- 1
Width, spacing and enclosure
Group violations by rule and repeated location pattern.
- 2
Density checks
Inspect the shapes and neighboring layers.
- 3
Violation debugging
Fix the generating placement or routing cause when possible.
- 4
Width, spacing and enclosure
Rerun incremental DRC, then full-chip signoff.
Explore each topic
01Width, spacing and enclosure
Understand the concept, connect it to the ASIC flow, study the report or behavior it produces, and apply it in a guided exercise. Check the result against the module goal before moving forward.
02Density checks
Understand the concept, connect it to the ASIC flow, study the report or behavior it produces, and apply it in a guided exercise. Check the result against the module goal before moving forward.
03Violation debugging
Understand the concept, connect it to the ASIC flow, study the report or behavior it produces, and apply it in a guided exercise. Check the result against the module goal before moving forward.
Completion checklist
- ✓ No waived error lacks approval
- ✓ Fixes do not create new violations
- ✓ Density checks are included
- ✓ Final deck is the release version
Practise with open-source tools
These are official third-party GitHub projects selected for this learning path.