Sequential design
Sequential circuits store state, so their output depends on current inputs and the previously captured value.
State changes only at the intended clock edge, and data must satisfy setup and hold around that edge.
A modulo-4 counter needs two flip-flops. On each rising edge, count <= count + 1; reset returns the state to 00.
Digital Design & Verilog flow
Follow each stage in sequence. Every stage produces information needed by the next.
Sequential design—visualized
This technical view uses the actual structures and relationships associated with this stage, followed by its key terms.
Understand every concept
Latches and flip-flops
What it is: Latches and flip-flops is a core concept within Sequential design. It describes the information, structure, or analysis engineers use at this stage of the Digital Design & Verilog flow.
Why it matters: Understanding it helps you interpret the stage correctly, avoid incorrect assumptions, and connect the result to the next implementation or signoff step.
Where it fits: This topic belongs to module 2, Sequential design, and its output supports the stages that follow.
Practical example: Engineer workflow: Define the state that must be remembered. A modulo-4 counter needs two flip-flops. On each rising edge, count <= count + 1; reset returns the state to 00.
Counters and registers
What it is: Counters and registers is a core concept within Sequential design. It describes the information, structure, or analysis engineers use at this stage of the Digital Design & Verilog flow.
Why it matters: Understanding it helps you interpret the stage correctly, avoid incorrect assumptions, and connect the result to the next implementation or signoff step.
Where it fits: This topic belongs to module 2, Sequential design, and its output supports the stages that follow.
Practical example: Engineer workflow: Choose registers and a reset strategy. A modulo-4 counter needs two flip-flops. On each rising edge, count <= count + 1; reset returns the state to 00.
Setup, hold and clocking basics
What it is: Setup, hold and clocking basics is a core concept within Sequential design. It describes the information, structure, or analysis engineers use at this stage of the Digital Design & Verilog flow.
Why it matters: Understanding it helps you interpret the stage correctly, avoid incorrect assumptions, and connect the result to the next implementation or signoff step.
Where it fits: This topic belongs to module 2, Sequential design, and its output supports the stages that follow.
Practical example: Engineer workflow: Describe next-state logic separately from state storage. A modulo-4 counter needs two flip-flops. On each rising edge, count <= count + 1; reset returns the state to 00.
Work through it step by step
- 1
Latches and flip-flops
Define the state that must be remembered.
- 2
Counters and registers
Choose registers and a reset strategy.
- 3
Setup, hold and clocking basics
Describe next-state logic separately from state storage.
- 4
Latches and flip-flops
Check waveforms at every active clock edge.
Explore each topic
01Latches and flip-flops
Understand the concept, connect it to the ASIC flow, study the report or behavior it produces, and apply it in a guided exercise. Check the result against the module goal before moving forward.
02Counters and registers
Understand the concept, connect it to the ASIC flow, study the report or behavior it produces, and apply it in a guided exercise. Check the result against the module goal before moving forward.
03Setup, hold and clocking basics
Understand the concept, connect it to the ASIC flow, study the report or behavior it produces, and apply it in a guided exercise. Check the result against the module goal before moving forward.
Completion checklist
- ✓ One clocking style is used consistently
- ✓ Reset behavior is explicit
- ✓ No combinational feedback exists
- ✓ All states have defined transitions
Practise with open-source tools
These are official third-party GitHub projects selected for this learning path.