BANZSASIC FLOW WORKSHOP← BackGet startedFoundation learning path
Digital Design & Verilog
Start with the digital-design concepts used throughout ASIC development, then express those ideas as clean, synthesizable Verilog.
6 weeks suggested pace4 modules structured sequence
Ask about this pathCurriculum
Follow the path, module by module.
Open every module for the full step-by-step lesson, examples, checklist, and next/previous navigation.
01020304
Digital foundations Open lesson →
- Number systems and Boolean algebra
- Logic gates and minimization
- Combinational building blocks
Sequential design Open lesson →
- Latches and flip-flops
- Counters and registers
- Setup, hold and clocking basics
Verilog RTL Open lesson →
- Modules, ports and data types
- Combinational and sequential coding
- Parameters and generate blocks
Design practice Open lesson →
- FSM architecture
- FIFO design
- Lint and synthesis-ready coding
Before you begin
Prerequisites
- Basic mathematics
- Curiosity about digital hardware
Ready to begin Digital Design & Verilog?
Write to us for the next learning schedule or workshop batch.
asicflowworkshop@gmail.com