Design practice
Small projects connect specification, architecture, RTL, simulation, and synthesis into one repeatable design process.
Separate control from datapath and define interfaces before writing implementation code.
A synchronous FIFO combines memory, read/write pointers, full/empty logic, and assertions that prevent illegal access.
Digital Design & Verilog flow
Follow each stage in sequence. Every stage produces information needed by the next.
Design practice—visualized
This technical view uses the actual structures and relationships associated with this stage, followed by its key terms.
Understand every concept
FSM architecture
What it is: FSM architecture is a core concept within Design practice. It describes the information, structure, or analysis engineers use at this stage of the Digital Design & Verilog flow.
Why it matters: Understanding it helps you interpret the stage correctly, avoid incorrect assumptions, and connect the result to the next implementation or signoff step.
Where it fits: This topic belongs to module 4, Design practice, and its output supports the stages that follow.
Practical example: Engineer workflow: Turn requirements into inputs, outputs, states, and corner cases. A synchronous FIFO combines memory, read/write pointers, full/empty logic, and assertions that prevent illegal access.
FIFO design
What it is: FIFO design is a core concept within Design practice. It describes the information, structure, or analysis engineers use at this stage of the Digital Design & Verilog flow.
Why it matters: Understanding it helps you interpret the stage correctly, avoid incorrect assumptions, and connect the result to the next implementation or signoff step.
Where it fits: This topic belongs to module 4, Design practice, and its output supports the stages that follow.
Practical example: Engineer workflow: Sketch the datapath and controller. A synchronous FIFO combines memory, read/write pointers, full/empty logic, and assertions that prevent illegal access.
Lint and synthesis-ready coding
What it is: Lint and synthesis-ready coding is a core concept within Design practice. It describes the information, structure, or analysis engineers use at this stage of the Digital Design & Verilog flow.
Why it matters: Understanding it helps you interpret the stage correctly, avoid incorrect assumptions, and connect the result to the next implementation or signoff step.
Where it fits: This topic belongs to module 4, Design practice, and its output supports the stages that follow.
Practical example: Engineer workflow: Implement one block at a time with a testbench. A synchronous FIFO combines memory, read/write pointers, full/empty logic, and assertions that prevent illegal access.
Work through it step by step
- 1
FSM architecture
Turn requirements into inputs, outputs, states, and corner cases.
- 2
FIFO design
Sketch the datapath and controller.
- 3
Lint and synthesis-ready coding
Implement one block at a time with a testbench.
- 4
FSM architecture
Integrate, regress, lint, and review synthesis results.
Explore each topic
01FSM architecture
Understand the concept, connect it to the ASIC flow, study the report or behavior it produces, and apply it in a guided exercise. Check the result against the module goal before moving forward.
02FIFO design
Understand the concept, connect it to the ASIC flow, study the report or behavior it produces, and apply it in a guided exercise. Check the result against the module goal before moving forward.
03Lint and synthesis-ready coding
Understand the concept, connect it to the ASIC flow, study the report or behavior it produces, and apply it in a guided exercise. Check the result against the module goal before moving forward.
Completion checklist
- ✓ Corner cases have tests
- ✓ Interfaces use consistent handshakes
- ✓ Assertions protect illegal states
- ✓ Reports contain no unexplained warnings
Practise with open-source tools
These are official third-party GitHub projects selected for this learning path.