Verification planning
A verification plan converts each requirement into a stimulus, checker, and measurable coverage target.
If a feature is not connected to a test and coverage point, completion cannot be demonstrated.
For a FIFO, plan simultaneous read/write, boundary depths, overflow, underflow, reset during traffic, and pointer wraparound.
Design Verification flow
Follow each stage in sequence. Every stage produces information needed by the next.
Verification planning—visualized
This technical view uses the actual structures and relationships associated with this stage, followed by its key terms.
Understand every concept
Specification review
What it is: Specification review is a core concept within Verification planning. It describes the information, structure, or analysis engineers use at this stage of the Design Verification flow.
Why it matters: Understanding it helps you interpret the stage correctly, avoid incorrect assumptions, and connect the result to the next implementation or signoff step.
Where it fits: This topic belongs to module 1, Verification planning, and its output supports the stages that follow.
Practical example: Engineer workflow: Extract features and corner cases from the specification. For a FIFO, plan simultaneous read/write, boundary depths, overflow, underflow, reset during traffic, and pointer wraparound.
Test planning
What it is: Test planning is a core concept within Verification planning. It describes the information, structure, or analysis engineers use at this stage of the Design Verification flow.
Why it matters: Understanding it helps you interpret the stage correctly, avoid incorrect assumptions, and connect the result to the next implementation or signoff step.
Where it fits: This topic belongs to module 1, Verification planning, and its output supports the stages that follow.
Practical example: Engineer workflow: Classify normal, error, stress, and interaction scenarios. For a FIFO, plan simultaneous read/write, boundary depths, overflow, underflow, reset during traffic, and pointer wraparound.
Directed vs constrained-random testing
What it is: Directed vs constrained-random testing is a core concept within Verification planning. It describes the information, structure, or analysis engineers use at this stage of the Design Verification flow.
Why it matters: Understanding it helps you interpret the stage correctly, avoid incorrect assumptions, and connect the result to the next implementation or signoff step.
Where it fits: This topic belongs to module 1, Verification planning, and its output supports the stages that follow.
Practical example: Engineer workflow: Define checkers and coverage for each item. For a FIFO, plan simultaneous read/write, boundary depths, overflow, underflow, reset during traffic, and pointer wraparound.
Work through it step by step
- 1
Specification review
Extract features and corner cases from the specification.
- 2
Test planning
Classify normal, error, stress, and interaction scenarios.
- 3
Directed vs constrained-random testing
Define checkers and coverage for each item.
- 4
Specification review
Track failures and coverage back to the plan.
Explore each topic
01Specification review
Understand the concept, connect it to the ASIC flow, study the report or behavior it produces, and apply it in a guided exercise. Check the result against the module goal before moving forward.
02Test planning
Understand the concept, connect it to the ASIC flow, study the report or behavior it produces, and apply it in a guided exercise. Check the result against the module goal before moving forward.
03Directed vs constrained-random testing
Understand the concept, connect it to the ASIC flow, study the report or behavior it produces, and apply it in a guided exercise. Check the result against the module goal before moving forward.
Completion checklist
- ✓ Every requirement has an owner
- ✓ Negative cases are included
- ✓ Coverage has a clear closure target
- ✓ The plan is reviewed before implementation
Practise with open-source tools
These are official third-party GitHub projects selected for this learning path.