Assertions & coverage
Assertions catch temporal rule violations, while coverage measures which planned behavior has actually occurred.
Assertions answer 'did anything illegal happen?' and coverage answers 'did we exercise what matters?'.
An assertion can require req to remain high until ack; a coverpoint records response latency from one to eight cycles.
Design Verification flow
Follow each stage in sequence. Every stage produces information needed by the next.
Assertions & coverage—visualized
This technical view uses the actual structures and relationships associated with this stage, followed by its key terms.
Understand every concept
Immediate and concurrent assertions
What it is: Immediate and concurrent assertions is a core concept within Assertions & coverage. It describes the information, structure, or analysis engineers use at this stage of the Design Verification flow.
Why it matters: Understanding it helps you interpret the stage correctly, avoid incorrect assumptions, and connect the result to the next implementation or signoff step.
Where it fits: This topic belongs to module 3, Assertions & coverage, and its output supports the stages that follow.
Practical example: Engineer workflow: Write properties for protocol and design invariants. An assertion can require req to remain high until ack; a coverpoint records response latency from one to eight cycles.
Code coverage
What it is: Code coverage is a core concept within Assertions & coverage. It describes the information, structure, or analysis engineers use at this stage of the Design Verification flow.
Why it matters: Understanding it helps you interpret the stage correctly, avoid incorrect assumptions, and connect the result to the next implementation or signoff step.
Where it fits: This topic belongs to module 3, Assertions & coverage, and its output supports the stages that follow.
Practical example: Engineer workflow: Add coverpoints for important values and transitions. An assertion can require req to remain high until ack; a coverpoint records response latency from one to eight cycles.
Functional coverage
What it is: Functional coverage is a core concept within Assertions & coverage. It describes the information, structure, or analysis engineers use at this stage of the Design Verification flow.
Why it matters: Understanding it helps you interpret the stage correctly, avoid incorrect assumptions, and connect the result to the next implementation or signoff step.
Where it fits: This topic belongs to module 3, Assertions & coverage, and its output supports the stages that follow.
Practical example: Engineer workflow: Cross only dimensions whose interaction matters. An assertion can require req to remain high until ack; a coverpoint records response latency from one to eight cycles.
Work through it step by step
- 1
Immediate and concurrent assertions
Write properties for protocol and design invariants.
- 2
Code coverage
Add coverpoints for important values and transitions.
- 3
Functional coverage
Cross only dimensions whose interaction matters.
- 4
Immediate and concurrent assertions
Review uncovered bins and add targeted stimulus.
Explore each topic
01Immediate and concurrent assertions
Understand the concept, connect it to the ASIC flow, study the report or behavior it produces, and apply it in a guided exercise. Check the result against the module goal before moving forward.
02Code coverage
Understand the concept, connect it to the ASIC flow, study the report or behavior it produces, and apply it in a guided exercise. Check the result against the module goal before moving forward.
03Functional coverage
Understand the concept, connect it to the ASIC flow, study the report or behavior it produces, and apply it in a guided exercise. Check the result against the module goal before moving forward.
Completion checklist
- ✓ Properties have clear clock and reset semantics
- ✓ Coverage bins map to the plan
- ✓ Illegal bins are intentional
- ✓ Vacuum passes are reviewed
Practise with open-source tools
These are official third-party GitHub projects selected for this learning path.