Intermediate engineering notes from the ASIC flow.

Short technical lessons that connect textbook concepts to the reports and decisions used during implementation.

LEVELIntermediate readsFORMAT8–12 min eachLEARNING MODEConcept + practice

Choose your focus

Intermediate content with a clear next action.

Each option includes technical topics, applied practice and a direct path to continue learning.

Ideal clocks hide insertion delay and real skew. After CTS, propagated clocks change launch/capture relationships and expose clock DRVs.

High local pin density, narrow macro channels and aggressive utilization can make a routable-looking floorplan fail later.

A good review checks constraint coverage and warnings before celebrating area, WNS or TNS numbers.

How to use this page

1
Before reading
Write your current answer to the article’s main question in two sentences.
2
During reading
Connect every term to a report field, command output or design structure.
3
After reading
Complete related assignments and explain one example without looking at the article.

160 INTERACTIVE QUESTIONS

Choose an answer, see correct responses in green, incorrect responses in red, and learn from the explanation.

Tell us what you want to learn, practise, or prepare for.